Σ/Δ ADC

Σ/Δ ADC resolution	16 bit	24 bit
Clock frequency	32 MHz	2 MHz
Sample rate	1 MSPS	16 KSPS
Integral nonlinearity	±2 LSB	±0,2% FS
Differential nonlinearity	±1 LSB	No missing codes
Min Effective number of bits	14.5 bits	12 bits
Input signal bandwidth	500 kHz	8 kHz

Highlights

Fully differential architecture

Linear phase response

Mash architecture                 

Parallel digital output

Applications

Sensor transducers and transmitters

Analog input modules

Temperature controllers

Climate chambers